1. Field of the Disclosure
The present disclosure relates to electronic devices, more particularly, to forming electronic devices with regions of different stresses and material compositions.
2. Description of the Related Art
Carrier mobility within an electronic component (e.g. a transistor) of an electronic device can be affected by the properties of the material from which the electronic component is formed. Such properties can include material composition, stress, crystal orientation, or any combination thereof. A change that improves the mobility for one carrier type can be detrimental to the mobility of a carrier of an opposing carrier type. Thus, in complementary metal-oxide semiconductor (“CMOS”) electronic devices, active regions having different sets of material properties may be used
One proposed method of achieving different sets of material properties can include epitaxially growing a first layer of 120 nm or thicker silicon germanium (“Si(x)Ge(1−x)”) on a silicon wafer and annealing the silicon wafer to relax the stress in the first layer. A second layer of silicon formed over the relaxed Si(x)Ge(1−x) can then have a tensile stress. Annealing a stressed film, such as the first layer, can cause surface roughening, dislocation defects within the film, or any combination thereof. Such a process could require additional processing, such as chemical mechanical polishing (“CMP”) of the surface or formation of additional Si(x)Ge(1−x) to form a layer of sufficient quality to form a semiconductor component.
Another method can be to form a first graded layer of Si(x)Ge(1−x) such that x can be close to 1 when formation of the layer begins, and gradually decrease as the layer thickens such that dislocation formation can be minimized. Once the desired concentration is reached, a thickness of relatively defect-free Si(x)Ge(1−x) can be formed, and a stressed silicon layer can be formed over the first graded layer. Such a layer can then be transferred to another wafer by a wafer bonding and cleaving process. The stress in a film like the first graded layer can cause hillocks or surface roughening during the formation of the semiconductor layers or subsequent processing, possibly requiring a CMP process be performed on Si(x)Ge(1−x) in order to facilitate the wafer bonding process.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention. The use of the same reference symbols in different drawings indicates similar or identical items.